1. Technical Field
The present invention relates generally to a semiconductor apparatus, and in particular to a 3D (three-dimensional) semiconductor apparatus that employs through vias.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus, in which a plurality of chips are stacked and packaged to increase the degree of integration, has been developed. In the 3D semiconductor apparatus, since two or more chips are vertically stacked, a maximum degree of integration may be achieved in the same area.
Various methods may be applied to realize the 3D semiconductor apparatus. In one of the methods, a plurality of chips having the same structure are stacked and are then connected with one another using wires, such as metal lines, such that the plurality of chips may operate as one semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which through-silicon vias are formed to pass through a plurality of stacked chips so that all the chips are electrically connected with one another. In the TSV type semiconductor apparatus, because the through-silicon vias vertically pass through the respective chips to electrically connect them with one another, the area of a package may be effectively reduced when compared to a semiconductor apparatus in which respective chips are connected with one another through peripheral wiring using wires.
TSVs are formed by filling via holes, which are defined through a dielectric substance, with a conductive material. Since the TSVs serve as a means for electrically connecting the stacked chips, in order to manufacture a good quality semiconductor apparatus, it is essential to test whether the TSVs are properly formed.
FIG. 1 is a schematic view of a test circuit for a semiconductor apparatus known in the art. The semiconductor apparatus includes first and second chips CHIP1 and CHIP2, and the test circuit includes a test pad 10, a through via selection unit 20, and a driver 30. The test pad 10 applies a test voltage Vmeas to a through via VIA in a test operation, and measures the amount of current Imeas that flows through the through via VIA. The through via selection unit 20 selects the through via VIA to which the test voltage Vmeas is to be applied, in response to a test control signal TC. The through via selection unit 20 includes a pass gate that is turned on by the test control signal TC.
The driver 30 forms a current path in response to the test control signal TC. The driver 30 includes a MOS transistor that receives the test control signal TC through the gate thereof, and connects the through via VIA with a ground potential. Accordingly, if the through via selection unit 20 and the driver 30 are turned on by the test control signal TC, a current path is formed from the test pad 10 through the driver 30. As the test pad 10 applies the test voltage Vmeas, current flows through the through via selection unit 20, the through via VIA, and the driver 30, and the test pad 10 can then measure the amount of current Imeas.
By measuring the amount of current Imeas, the resistance value of the through via VIA may be calculated from the following equations:Rdrv+Rtsv+Rpg=Vmeas/ImeasRtsv=Vmeas/Imeas−(Rdrv+Rpg)
Where Rdrv is the ON resistance of the driver 30, Rtsv is the resistance value of the through via VIA, and Rpg is the ON resistance of the pass gate included in the selection unit 20.
As can be appreciated from the above equations, Rtsv depends on Rdrv and Rpg. However, in general, since the resistance of the through via VIA is substantially smaller than the ON resistance of the pass gate and the driver 30, and the characteristics of these devices may change due to a variation in process, etc., it is difficult to measure the resistance of the through via VIA with precision.